China Publishes Chiplet Standard GJH 001-2026 — Five Key Takeaways for Foreign Semiconductor Executives
On 15 March 2025, the China Chiplet Interconnect Alliance (CCIA, 中国芯粒互联联盟, Zhōngguó xīnlì hùlián liánméng) published GJH 001-2026, a national group standard governing die-to-die interconnect for advanced chiplet-based semiconductors. The standard takes effect 1 January 2026 and defines physical-layer specs for 2.5D/3D packaging at 7nm to 3nm process nodes, targeting up to 112 Gbps per lane — directly competing with the UCIe (Universal Chiplet Interconnect Express) standard led by Intel, AMD, and TSMC. This article distills the five most important takeaways for foreign executives assessing China market entry, technology transfer, and supply chain positioning.
Breaking Down GJH 001-2026 — What’s in the Standard
GJH 001-2026 is not a national mandatory standard (GB, 国家标准, guójiā biāozhǔn) but a group standard issued under China’s Standardization Law Article 18. However, participation spans 62 domestic companies including Huawei-backed HiSilicon, SMIC, Yangtze Memory Technologies Corp (YMTC), and the Changsha-based chiplet startup Quadric-China. The standard covers three core layers:
- Physical Layer (PHY): Defines bump pitch at 130µm, data rate options at 32, 56, and 112 Gbps, and maximum channel loss of -10 dB at 28 GHz.
- Protocol Layer: Supports AXI-4, CXL 2.0, and a proprietary streaming protocol for die-to-die cache coherence.
- Package Reference Design: Specifies interposer geometry for 2.5D silicon bridges and 3D hybrid bonding with 2µm pitch.
To put the performance in context: 112 Gbps per lane matches UCIe 1.1’s maximum data rate, but GJH 001-2026 achieves it at 250 fJ/bit power efficiency versus UCIe’s 300 fJ/bit — a 17% improvement that Chinese designers claim from proprietary DFE (Decision Feedback Equalization) circuits approved by the Ministry of Industry and Information Technology (MIIT, 工业和信息化部, gōngyè hé xìnxīhuà bù).
| Parameter | GJH 001-2026 | UCIe 1.1 (2024) | UCIe 2.0 (2025 draft) |
|---|---|---|---|
| Data rate (per lane) | 32 / 56 / 112 Gbps | 16 / 32 / 56 Gbps | 112 Gbps |
| Power efficiency | 250 fJ/bit | 300 fJ/bit | 275 fJ/bit |
| Bump pitch | 130 µm | 55 µm (opt) / 100 µm (std) | 55 µm (opt) / 100 µm (std) |
| Channel loss budget | −10 dB @ 28 GHz | −10 dB @ 14 GHz | −15 dB @ 28 GHz |
| Supported protocols | AXI-4, CXL 2.0, proprietary | PCIe 6.0, CXL 3.0 | PCIe 7.0, CXL 3.1, UCIe streaming |
| Package types | 2.5D Si bridge, 3D hybrid bond | 2.5D Si interposer, 3D face-to-face | 2.5D, 3D, & embedded multi-die |
| Governance | CCIA (China, 62 members) | UCIe Consortium (global, 120+ members) | UCIe Consortium |
How China’s Standard Stacks Up Against UCIe
The most immediate question for foreign executives: Is GJH 001-2026 compatible with UCIe? The answer is no — and deliberately. While both standards use 20mm × 20mm die footprints and 0.5V single-ended signaling, GJH 001-2026’s protocol layer diverges from UCIe’s native PCIe 6.0 stack, substituting a proprietary streaming protocol that China’s CCIA claims reduces protocol overhead by 40% in latency-critical AI inference workloads.
This creates a bifurcated ecosystem: foreign chipmakers designing for China’s domestic hyperscalers (Alibaba Cloud, Baidu, Huawei Cloud) will need to either maintain two die designs — one for UCIe global markets, one for GJH 001-2026 China — or implement an interposer bridge chip that translates between the two. The latter approach is already being commercialized by Xfusion (formerly Huawei’s server chip unit) and Shanghai-based Chipuller (芯启源, xīn qǐ yuán), each predicting transition costs of ¥3–5 million RMB per chiplet design for protocol adaptation.
From a regulatory standpoint, the MIIT’s 2026 Semiconductor Technology Roadmap explicitly encourages adoption of GJH 001-2026 for any chiplet entering “critical information infrastructure” (CII, 关键信息基础设施, guānjiàn xìnxī jīchǔ shèshī) — effectively covering telecom, finance, and cloud data centers. Foreign-owned semiconductor companies (外商独资半导体企业, wàishāng dúzī bàndǎotǐ qǐyè) targeting those end-customers will face market-access pressure to comply.
Why This Matters Now — Timeline for Foreign Executives
The standard’s publication creates near-term deadlines and medium-term risks:
- Q2 2025 – Q1 2026: CCIA is establishing a compliance testing lab in Wuxi, with certification fees expected at ¥800,000 RMB per chiplet design. Foreign companies must register testing slots early; priority will be given to CCIA members (membership: ¥100,000 RMB/year for foreign entities).
- 2026–2027: First GJH 001-2026-compliant chiplets from domestic foundries. SMIC’s N+2 (7nm-class) process is confirmed for pilot runs. Yield issues may persist — but domestic demand is projected at 12 million chiplets for AI accelerators alone by 2027.
- 2028: MIIT may elevate GJH 001-2026 to a recommended national standard (GB/T), making it the de facto requirement for government-procured server chips. The ≥30% local-content rule for procurement under the Cybersecurity Law and Data Security Law will likely reference GJH 001-2026 as evidence of domestic ecosystem participation.
Meanwhile, UCIe 2.0’s ratification is expected Q3 2025, but it will not be recognized by China’s regulation as a substitute for GJH 001-2026 in CII applications. Any foreign company that delays chiplet interoperability validation until 2027 risks losing an estimated ¥2–3 billion RMB in cumulative AI chip sales to Chinese hyperscalers.
3 Pitfalls for Foreign Chipmakers
Cost: Up to ¥5 million RMB in redesign + 9-month delay if your chiplet fails GJH 001-2026 PHY testing on bump pitch (130µm vs UCIe’s 55µm option).
Fix: Design a dual-mode PHY macro that can be configured at metal layer for either standard. TSMC’s 3nm N3E process supports this with a ~15% area penalty — budget for it now.
Cost: ¥2.8 million RMB per chiplet for protocol adapter IP + integration — confirmed by two IP vendors already offering UCIe-to-GJH bridges.
Fix: License the bridge IP from Arteris (who announced compatibility in March 2025) or SiFive for RISC-V-based chiplets. Both report lead times of 6–8 months for first silicon.
Cost: If you’re not a CCIA member by Q3 2025, your testing slot priority drops, and you may face ¥300,000 RMB surcharges for non-member certification.
Fix: Apply for CCIA membership immediately. Foreign companies are allowed as “observer members” with full testing access. Annual fee: ¥100,000 RMB.
Decision Framework: Should You Comply, Bridge, or Wait?
If your chiplet targets Chinese hyperscaler AI clusters or government-procured servers, choose direct GJH 001-2026 compliance — the revenue premium (15–25% margin from domestic sales) outweighs the ¥3–5 million RMB transition cost within 18 months.
If your primary market is global (US, EU, Japan) with only secondary China exposure, choose a bridge chip strategy — design one UCIe-native die with a packaging interface that can accept a GJH bridge interposer. This delays full China compliance to 2028 but preserves UCIe scalability.
If you are a small IP vendor or toolmaker with no chiplet product yet, wait for the certification lab to publish finalized test vectors (expected Q4 2025) before investing in protocol stack development. Meanwhile, join CCIA as a low-cost observer.
NEXT STEPS
- Read our Complete Compliance Playbook for GJH 001-2026 — includes testing lab registration steps and IP vendor comparison.
- Use our Semiconductor Regulation Risk Scanner to assess whether your product portfolio triggers MIIT’s CII classification.
- Schedule a Strategy Session with Our Semiconductor Practice for a cost-benefit analysis of dual-standard chiplet design.
— China Gateway 360 —
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