How does China’s IP protection work for semiconductor?

Yes — China’s IP protection framework covers semiconductor innovations through patents, IC layout design protection (集成电路布图设计, jíchéng diànlù bùtú shèjì), and trade secrets, with over 80,000 IC layout design registrations filed at CNIPA as of 2025 and more than 4,100 semiconductor invention patent grants in 2024 alone. Foreign semiconductor companies can protect chip architectures, fabrication methods, circuit layouts, and proprietary EDA tools under PRC law, though the system imposes specific procedural requirements — including mandatory filing through a CNIPA-registered agency for applicants without a Chinese business address (Patent Law Article 18) — and distinct timelines that differ materially from US or European practice.

Direct Answer: IP Protection for Semiconductors in China

China offers a multi-layered IP protection regime tailored to the semiconductor industry. The framework combines patent protection for inventions and process innovations, a specialized sui generis system for integrated circuit layout designs (集成电路布图设计保护条例, jíchéng diànlù bùtú shèjì bǎohù tiáolì), and trade secret protection under the PRC Anti-Unfair Competition Law (反不正当竞争法, fǎn bùzhèngdàng jìngzhēng fǎ). According to CNIPA (国家知识产权局, guójiā zhīshì chǎnquán jú) statistics, China received over 1.5 million patent applications in 2024, with semiconductor-related filings representing a growing share driven by national IC industry policy and the RMB 344 billion National IC Fund Phase III.

The 2020 amendments to the PRC Patent Law (专利法, zhuānlì fǎ), effective June 1, 2021, introduced key changes relevant to semiconductor innovators: increased statutory damages for patent infringement to RMB 5 million (approximately USD 690,000), introduced punitive damages for willful infringement at up to five times the actual loss, and created an open licensing framework. For foreign semiconductor companies, the practical question is not whether protection exists, but how to navigate the registration procedures, enforcement landscape, and strategic trade-offs between different protection types.

Types of IP Protection Available

Semiconductor innovations can be protected through four distinct IP mechanisms in China, each with different subject matter, duration, and procedural requirements:

For most semiconductor companies, a combination strategy is optimal. Invention patents should be filed for novel fabrication methods and circuit architectures. IC layout design registration protects the specific topographical arrangement of circuit elements — a protection category that patent systems alone do not adequately cover. Trade secret protection serves as a fallback and complement for proprietary know-how disclosed to limited personnel, such as process recipes and mask set configurations.

Foreign applicants without a Chinese business address must file patents, IC layout designs, and trademarks through a CNIPA-registered patent agency (专利代理机构, zhuānlì dàilǐ jīgòu), as prescribed by Patent Law Article 18. The agency handles translation, filing, and prosecution communications with CNIPA. Choosing an agency with semiconductor technical expertise — particularly one familiar with the CNIPA Semiconductor Examination Department — materially affects prosecution outcomes.

Patent Protection for Semiconductor Inventions

The PRC Patent Law, as amended in 2020, provides the primary legal framework for semiconductor invention patents. Key provisions relevant to semiconductor innovators include:

• Patentability requirements (Article 22): Inventions must demonstrate novelty, inventiveness (an inventive step), and practical applicability. For semiconductor inventions, CNIPA examiners apply the “problem-solution” approach — comparing the claimed invention against the closest prior art to assess whether it would have been obvious to a person skilled in the art. The inventiveness threshold in China has risen in recent years, particularly for software-implemented inventions and algorithm-based EDA innovations.
• Patent term (Article 42): Invention patents receive 20 years from the filing date. The 2020 amendment introduced patent term compensation (专利期限补偿, zhuānlì qīxiàn bǔcháng) of up to five years for unreasonable delays in the examination process, and a separate extension of up to five years for pharmaceutical patents — though the latter does not apply to semiconductor patents.
• Open licensing (Article 50-52): A new voluntary open licensing system introduced in 2021 allows patent holders to declare willingness to license on publicly stated terms, with reduced annual maintenance fees. This is relevant for semiconductor standard-essential patents (SEPs) and may facilitate FRAND licensing negotiations.
• Compulsory licensing (Articles 48-58): The Patent Law retains provisions for compulsory licensing in cases of national emergency, public interest, or failure to exploit without reasonable grounds. Compulsory licenses for semiconductor patents carry additional restrictions under TRIPS Article 31 — they may only be granted for public non-commercial use or to remedy anti-competitive practices.

Patent examination timelines vary significantly by patent type. Understanding these timelines is critical for semiconductor companies planning market entry or product launches in China:

CNIPA’s Patent Prosecution Highway (PPH) program allows semiconductor applicants with a corresponding patent allowed or granted in participating patent offices (USPTO, JPO, KIPO, EPO) to request accelerated examination in China. As of 2025, CNIPA reported that PPH requests reduced average first office action time from 16 months to approximately 8 months for participating applications.

For software-implemented semiconductor inventions — a common category in EDA and design automation — CNIPA’s Patent Examination Guidelines (2023 revision) provide detailed guidance on computer-implemented inventions (计算机实施的发明, jìsuànjī shíshī de fāmíng). The key requirement is that the claimed invention must produce a “technical effect” (技术效果, jìshù xiàoguǒ) in a technical field, rather than solving a purely mathematical or business problem. Claims directed to layout optimization algorithms, parasitic extraction methods, and timing analysis tools should emphasize the concrete technical improvement — such as reduced chip area, lower power consumption, or improved signal integrity — to satisfy CNIPA examiners.

IC Layout Design Protection

China’s Regulations on the Protection of IC Layout Designs (集成电路布图设计保护条例, jíchéng diànlù bùtú shèjì bǎohù tiáolì), enacted in 2001 and modeled on the TRIPS Article 35-38 framework, provide a sui generis system specifically designed for integrated circuit topographies. This is one of the most important — and most underutilized — IP protection mechanisms available to foreign semiconductor companies operating in China.

Key features of IC layout design protection include:

1. No novelty requirement: Unlike patents, IC layout design registration does not require absolute worldwide novelty. The layout need only be “original” (原创性, yuánchuàngxìng) in the sense that it is the result of the creator’s own intellectual effort and not commonplace among IC designers at the time of creation. This lower threshold makes registration faster and more predictable than patent prosecution.
2. Term of protection: 10 years from the date of filing with CNIPA or the date of first commercial exploitation anywhere in the world, whichever is earlier. Protection lapses if the layout design has not been commercially exploited within 15 years of its first fixation in a tangible form.
3. Scope of protection: The right holder has the exclusive right to reproduce the protected layout design in whole or in part (except for reproduction for evaluation, analysis, research, or teaching purposes — the “reverse engineering” exception), and to import, sell, or otherwise distribute the integrated circuit embodying the protected layout design.
4. Registration procedure: Filing is straightforward compared to patent prosecution. Applicants submit drawings or photographs of the layout design (typically mask set layers), along with a brief description. CNIPA conducts a formal examination only — no substantive examination of originality — and registration typically completes within 3–6 months. Official fees are modest, approximately RMB 2,000 per registration.
5. Reverse engineering exception (Article 23): Reproduction of a protected layout design for the purpose of evaluation, analysis, research, or teaching is explicitly permitted. The results of such analysis — if they produce a new, original layout design — may be commercially exploited without infringement. This exception is critical for foreign semiconductor companies conducting competitive analysis or academic collaboration in China.

As of 2025, CNIPA had received over 80,000 IC layout design registrations cumulatively, with annual filings exceeding 5,000. However, enforcement actions based on IC layout design rights remain relatively rare — fewer than 50 reported court cases since 2001 — in part because proving unauthorized reproduction of a specific layout design requires detailed technical evidence, often involving reverse engineering and chip decapsulation. Foreign semiconductor companies should therefore view IC layout design registration as a complement to patent protection rather than a replacement.

Trade Secret Protection for Chip Designs

Trade secret protection (商业秘密保护, shāngyè mìmì bǎohù) has become an increasingly important pillar of semiconductor IP protection in China, particularly following the 2019 amendments to the PRC Anti-Unfair Competition Law (反不正当竞争法, fǎn bùzhèngdàng jìngzhēng fǎ) and the enactment of the PRC Data Security Law (数据安全法, shùjù ānquán fǎ) in 2021.

Under the Anti-Unfair Competition Law, a trade secret is defined as technical or business information that (a) is not known to the public, (b) has commercial value, and (c) is subject to reasonable confidentiality measures by the right holder. For semiconductor companies, qualifying trade secrets may include:

• Process recipes and fabrication parameters (e.g., doping concentrations, etch times, temperature profiles)
• Mask set configurations and reticle designs not yet filed for layout design registration
• EDA tool proprietary algorithms and cell library data
• Customer-specific design specifications and test protocols
• Yield optimization data and failure analysis methodologies

The 2019 amendments to the Anti-Unfair Competition Law significantly strengthened trade secret protection in several respects. First, they increased the maximum statutory damages to RMB 5 million (approximately USD 690,000) and introduced punitive damages of up to five times actual losses for willful misappropriation. Second, they shifted the burden of proof in certain circumstances — if the right holder provides初步 evidence (chūbù zhèngjù, preliminary evidence) of misappropriation and the accused party possesses the means to access the secret, the court may require the accused to prove they did not use the trade secret (Article 32). Third, they extended liability to individuals who “induce” or “aid” trade secret misappropriation, including employee poaching where the new employer knew or should have known of confidentiality obligations.

The Data Security Law (2021) adds an additional layer of compliance for semiconductor companies handling cross-border data transfers. Article 21 establishes a categorized data protection system, with “important data” (重要数据, zhòngyào shùjù) subject to cross-border transfer restrictions. For semiconductor companies, the definition of important data has been interpreted by MIIT (工业和信息化部, gōngyè hé xìnxīhuà bù) to include certain categories of semiconductor manufacturing data, design files, and yield statistics — particularly for advanced-node processes (<28nm). Companies transferring such data outside China must conduct a data export risk assessment and, in some cases, obtain regulatory approval.

For foreign semiconductor companies, practical trade secret protection measures in China should include: (a) written confidentiality agreements with employees and contractors that comply with PRC contract law; (b) restricted physical and logical access to sensitive design and process data; (c) documented confidentiality markings on all technical documents; (d) employee exit procedures including return of materials and confirmation of confidentiality obligations; and (e) data localization measures to minimize cross-border transfer exposure under the Data Security Law.

Enforcement and Litigation

IP enforcement for semiconductor rights in China has evolved significantly over the past decade. CNIPA administers patent, trademark, and IC layout design registrations, while enforcement is handled through specialized IP courts (知识产权法院, zhīshì chǎnquán fǎyuàn), local people’s courts, and administrative enforcement actions.

China’s specialized IP court system — established in Beijing (2014), Shanghai (2014), Guangzhou (2014), and expanded to 22 IP tribunals across the country by 2025 — handles patent infringement cases, including semiconductor patent disputes. These courts have demonstrated increasing technical sophistication, with many judges holding science and engineering degrees and courts frequently appointing technical investigation officers (技术调查官, jìshù diàochá guān) to assist in evaluating complex semiconductor patent claims.

Key enforcement statistics for semiconductor-related IP in China:

• Patent litigation volume: CNIPA reported that patent infringement cases filed with Chinese courts exceeded 45,000 in 2024, with semiconductor-related cases estimated at 800–1,200 annually based on IPC class analysis
• Patent invalidation rate: Approximately 60% of invention patents challenged through CNIPA invalidation proceedings are either fully or partially invalidated — significantly higher than in US or European proceedings, making patent quality and claim drafting strategy critical for enforceability
• Average damages awarded: Median patent infringement damages in Chinese courts have risen from approximately RMB 200,000 (2015) to RMB 1.5–2 million (2024), with statutory maximum damages of RMB 5 million under the 2020 Patent Law amendments
• Preliminary injunctions: Chinese courts granted preliminary injunctions in approximately 15–20% of patent infringement requests in 2024, up from fewer than 5% a decade earlier, though semiconductor cases face higher evidentiary thresholds for demonstrating irreparable harm
• Administrative enforcement: Local IP offices handle approximately 30,000 administrative patent dispute cases annually, providing a faster (typically 3–6 months) and lower-cost alternative to court litigation, though administrative decisions are limited to cease-and-desist orders with no damages

For semiconductor patent owners, the invalidation rate at CNIPA presents a significant strategic risk. A 60% full or partial invalidation rate means that poorly drafted claims — particularly those that fail to clearly distinguish over prior art in the examination record — are highly vulnerable when asserted against competitors. Foreign semiconductor companies should: (a) invest in high-quality Chinese-language claim drafting by a CNIPA-registered agent with semiconductor expertise; (b) maintain a thorough prosecution history record; and (c) consider filing parallel utility model applications for fast-grant protection while invention patent prosecution proceeds over the 22-month timeline.

International Considerations

Foreign semiconductor companies must navigate the intersection of China’s domestic IP regime with international filing systems and home-country export controls.

PCT route (Patent Cooperation Treaty): Semiconductor inventions can be filed in China through the PCT national phase entry route (Patent Law Article 28). Applicants file an international application under the PCT, then enter the Chinese national phase within 30 months of the priority date. CNIPA serves as both a receiving office and an International Searching Authority (ISA) for PCT applications. The PCT route is the preferred filing strategy for most foreign semiconductor companies, providing a 30-month window to assess market potential before committing to CNIPA prosecution costs.

Paris Convention: For direct CNIPA filings, semiconductor applicants can claim priority from an earlier filing in a Paris Convention member state within 12 months of the first filing (Patent Law Article 29). CNIPA accepts electronic priority documents through WIPO’s Digital Access Service (DAS). All foreign priority documents must be accompanied by a certified Chinese translation of the priority application.

Hague Agreement for Designs: Since February 2022, China has been a member of the Hague Agreement Concerning the International Registration of Industrial Designs. Semiconductor design patents — covering chip package appearance, product housings, and graphical user interfaces — can be protected through a single international application designating China, eliminating the need for separate domestic filings.

Hague Apostille Convention (海牙 Apostille 公约, Hǎiyá Apostille gōngyuē): Since November 7, 2023, China has been a party to the Hague Apostille Convention, abolishing the requirement for consular legalization of foreign public documents. Documents required for semiconductor IP filings in China — including notarized powers of attorney, assignment agreements, and priority certificates — can now be authenticated through a simple apostille issued in the country of origin, reducing document preparation time from 4–6 weeks to approximately 1 week.

US/EU export control spillover: No discussion of China semiconductor IP protection is complete without acknowledging the extraterritorial impact of US and EU export controls. The US Bureau of Industry and Security (BIS) Entity List designations — affecting companies such as SMIC (中芯国际, zhōngxīn guójì) and YMTC (长江存储, chángjiāng cúnchǔ) — and Dutch/EU controls on ASML lithography equipment create a compliance environment where foreign semiconductor companies must simultaneously satisfy Chinese registration requirements and home-country technology transfer restrictions. The PRC Export Control Law (出口管制法, chūkǒu guǎnzhì fǎ, 2020) provides the legal basis for China’s retaliatory controls on gallium, germanium, antimony, and other critical minerals, and authorizes countermeasures against foreign companies that “violate international law or the basic norms of international relations” (Article 12). For foreign semiconductor companies, this means that IP filing and enforcement strategies must be coordinated with export control compliance programs across multiple jurisdictions.

Technology import contract registration (技术进口合同登记, jìshù jìnkǒu hétóng dēngjì) is an additional requirement under the Technology Import/Export Regulations. Any semiconductor technology or IP transferred from abroad into a China-based entity — including patent licenses, EDA tool licenses, and know-how disclosure — must be registered with the local MOFCOM department within 60 days of contract execution. Failure to register renders the technology import contract unenforceable and may prevent royalty remittance through SAFE channels.

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