Semiconductor Update: China’s EDA Tool Market Developments — Key Takeaways

Electronic Design Automation (EDA, 电子设计自动化, diànzǐ shèjì zìdònghuà) tools are the software backbone of the semiconductor industry, enabling the design, simulation, and verification of integrated circuits (集成电路, jíchéng diànlù). China’s EDA tool market has grown to an estimated ¥15 billion (~$2.1 billion) in 2024, reflecting the nation’s strategic push for semiconductor self-sufficiency amid tightening US export controls. This development signals critical shifts for foreign executives who rely on or compete within China’s semiconductor ecosystem.

EDA Market Size and Growth Dynamics

China’s EDA market has expanded at a compound annual growth rate (CAGR) of approximately 15% from 2020 to 2024, outpacing the global EDA market growth of 8% over the same period. The global EDA market is valued at roughly $15 billion in 2024, with China accounting for about 10% of that total, or $1.5 billion to $2 billion depending on the measurement methodology.

Several factors drive this growth. First, China now hosts over 3,000 integrated circuit (IC) design companies, according to the China Semiconductor Industry Association (CSIA). Each requires EDA tools for chip development, creating robust domestic demand. Second, government initiatives under the “Made in China 2025” (中国制造2025, zhōngguó zhìzào 2025) plan have allocated over ¥50 billion in subsidies since 2020 to support domestic EDA development and adoption.

Third, US export controls imposed since October 2022 have restricted Chinese access to advanced EDA tools from US-based vendors like Synopsys, Cadence, and Siemens EDA (formerly Mentor Graphics). This has forced Chinese firms to accelerate domestic alternatives, creating a captive market for local EDA providers. The Bureau of Industry and Security (BIS) regulations now require export licenses for EDA tools capable of designing chips at 7nm or below, directly impacting China’s advanced design capabilities.

The Rise of Domestic EDA Players

China’s domestic EDA ecosystem has grown from fewer than 30 companies in 2020 to over 120 active EDA firms in 2024, according to industry estimates from IC Insights China. Leading players include Empyrean Technology (华大九天, huádà jiǔtiān), which holds the largest domestic market share at an estimated 6% of China’s total EDA market, as well as PrimaSim (概伦电子, gàilún diànzǐ), Xpeedic (芯和半导体, xīnhé bàndǎotǐ), and others specializing in specific design domains.

Empyrean Technology, listed on the Shenzhen Stock Exchange in 2022, reported revenue of ¥860 million in 2023, up 35% year-over-year. The company focuses on analog and mixed-signal EDA tools, a segment where domestic firms have gained the most traction due to lower complexity compared to digital front-end tools. PrimaSim specializes in simulation and verification tools for advanced memory and logic chips, counting Yangtze Memory Technologies Corp (YMTC) among its key customers.

Despite this growth, domestic EDA tools command only about 15% market share in China as of 2024, up from roughly 5% in 2020. The remaining 85% is still dominated by Synopsys, Cadence, and Siemens EDA, although US export restrictions increasingly limit access to their latest versions for Chinese customers. This creates a market bifurcation: advanced node customers accept restricted tools, while mid-range and government-backed clients shift to domestic options.

Strategic Implications for Foreign Firms

For foreign executives, the EDA developments in China present both risks and opportunities. US-based EDA vendors face ongoing revenue pressure as Chinese clients seek alternatives or operate with restricted tool versions. Synopsys derived approximately 15% of its global revenue from China in fiscal 2023, and this share is declining due to export controls and substitution effects. Cadence reported similar trends, with China revenue falling from 18% to 12% of total sales between 2022 and 2024.

Foreign semiconductor companies designing chips for the Chinese market must evaluate whether their EDA toolchains can integrate with domestic alternatives. Several multinational firms have established joint ventures with Chinese EDA companies to develop hybrid workflows. For example, a European chipmaker recently partnered with a Shanghai-based EDA startup to co-develop RISC-V design tools optimized for domestic foundries. These partnerships allow foreign firms to maintain market access while complying with local content expectations.

Additionally, foreign EDA vendors exploring the Chinese market now face a bifurcated landscape: high-end customers still prefer international tools but face access barriers, while mid-range and government-backed clients increasingly mandate domestic tool usage. This creates openings for technology licensing and strategic alliances rather than direct sales. Executives should model scenarios where Chinese EDA tools achieve 25% domestic market share by 2026, reducing dependence on foreign vendors for non-critical design work.

Challenges to Self-Sufficiency

China’s path to EDA independence faces significant hurdles. The talent gap is acute: industry sources estimate China needs at least 5,000 specialized EDA engineers, but only about 2,000 are currently available. This shortage limits the pace of tool development and quality assurance. Chinese universities have expanded EDA-focused curricula since 2021, but graduates require 3-5 years of training before contributing effectively to complex tool development.

Advanced process nodes present another obstacle. Domestic EDA tools have achieved reasonable capability for 28nm and above process nodes, but remain 3-5 years behind international leaders for 7nm and below. Since TSMC and SMIC (中芯国际, zhōngxīn guójì) produce chips at advanced nodes, the EDA tool gap constrains China’s ability to design high-performance chips domestically. Huawei’s HiSilicon, for instance, has resorted to using domestic EDA tools for older node designs while maintaining restricted access to international tools for its few advanced projects.

Finally, the IP and ecosystem integration challenge is formidable. Modern EDA tools must interface with hundreds of foundry process design kits (PDKs), third-party IP blocks, and verification libraries. Chinese EDA firms are building these connections but at a slower pace than incumbents who have decades of integration experience. SMIC alone supports over 200 PDKs for various process nodes, and domestic EDA tools currently integrate with only about 40% of them, limiting designer flexibility.

NEXT STEPS

Foreign executives making China semiconductor decisions should take the following three steps to navigate the evolving EDA landscape:

1. Audit your EDA supply chain dependencies. Identify which tools and versions your China operations use, and assess whether export restrictions or local content requirements could disrupt your design workflows within 12-24 months. Map each tool against BIS export control categories and alternative domestic options.
2. Evaluate local partnership options. Engage with leading domestic EDA firms like Empyrean Technology and PrimaSim to explore co-development, licensing, or technology transfer arrangements that could ensure access continuity. Begin with non-critical design flows to test integration compatibility before committing to broader adoption.
3. Monitor policy timelines. Track China’s “14th Five-Year Plan” semiconductor targets and Ministry of Industry and Information Technology (MIIT) directives that may mandate domestic EDA usage percentages in government-backed chip projects. Plan for scenarios where 30% domestic tool usage becomes mandatory for AI, automotive, and defense chip designs by 2027.

— China Gateway 360 —

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